This invention relates generally to digital data communication systems, and more particularly to recovering clock signals and digital data from a serial data signal.
Modern data communication systems are required to accurately transmit and receive digital information at high data transmission rates. The digital information is often transmitted great distances over a variety of communication mediums such as electrically conducting wires and, commonly now, optical fibers. Great demands as to speed and reliability are placed on these systems. One measure of reliability of such systems is the bit error rate (BER) of the system, and modern communication systems are required to have exceedingly low bit error rates.
When a receiving unit in a data communication system receives a signal, generally an electrical or optical signal, containing digital information, the receiving unit must recover the digital information from the signal. In other words, if a transmitter transmits a signal containing information corresponding to a particular bit sequence, then the receiving unit must recover the particular bit sequence from the received signal.
In addition, often the received data signal does not include a separate clock signal or other direct indication of the demarcation within the signal between the separate bits making up the signal. For example, when bit sequences are transmitted in a non-return to zero (NRZ) format, a logic 1 bit is indicated by a signal at a first energy level, and a logic 0 bit is indicated by a signal at a second (usually lower) energy level. The clock signal used to define the bit sequence by demarcating the bits within the sequence is not explicitly transmitted to the receiving unit. Data formats, such as NRZ, which do not provide inherent demarcation between bits in the data stream are often preferred because such formats have greater bandwidth as clock information is not explicitly required to be transmitted. Accordingly, receiving units must generally be able to recover clock information from the received signal, and then use that recovered clock information to determine the bit sequences contained in the received signal.
Systems for recovering clock and data information from data communicated according to data formats such as an NRZ format are known. Often such systems use a phase locked loop (PLL) to determine a clock signal corresponding to the clock used to generate the data stream. PLLs use a clock generator generating a clock signal at what is hoped to be the same frequency as the clock frequency of the transmitter, and adjusts the phase of the generated clock signal to form a phase adjusted clock signal based on information implicitly contained in the data signal. Periodic transitions, generally positive edge transitions, of the phase adjusted clock signal are used as timing points at which the data signal is sampled by comparing the data signal to a set energy level. If the energy level, usually in volts, is above the set energy level a logic 1 bit is placed in the bit sequence. If the energy level is below the set energy level a logic 0 is placed in the bit sequence.
FIG. 1 illustrates dual semi-idealized digital waveforms of data signals. A y-axis represents voltage of the data signals, and an x-axis represents time. As illustrated, a waveform of a first data signal 11a represents a binary sequence of alternating logic 1s and 0s. A waveform of a second data signal 11b represents the complement of the alternating binary sequence of the first binary sequence. The waveforms deviate from ideal waveforms in that each has a finite rise time and fall time when transitioning to and from a logic level 1 and a logic level 0.
The waveforms are divisible over time into a number of data cells 15a-d. Each of the data cells 15a-d represents one bit of data in a sequence of bits. In order to reconstruct the transmitted binary sequence the data signal is sampled and compared once for each data cell, generally at the expected midpoint in time of the data cell. Sampling is performed at defined intervals, generally in what is expected to be the middle of the period of an idealized data cell. Comparing is accomplished by comparing an energy level, generally a voltage, of the data signal with a pre-defined energy level, or voltage, which is generally in the middle of the expected range of energy levels. Thus, if the first data signal 11a is sampled once in each of the data cells 15a-d at times 19a-d using a voltage reference 17, the resulting bit pattern is 0101. Similarly sampling the second data signal results in a bit pattern of 1010.
Such systems are prone to errors, however. Slight differences in frequency between the transmitter clock and the clock generator of the receiving unit may lead to data recovery errors over time, or at least require periodic reacquisition of the correct phase adjusted clock signal, with a loss of bandwidth during the reacquisition period. In addition, deviations from an ideal transmitted data signal and distortions in transmitted signals, whether generated by properties of the transmitter, the communication medium, or otherwise, may result in data recovery errors. There are many causes of such deviations and distortions, and the deviations may change from transmitted bit to transmitted bit as well as exhibit both drift and an increase in the magnitude of the deviations over time as components age.
The transmitter may transmit signals that deviate from the ideal in terms of rise time, fall time, and energy levels. These deviations may vary from transmitter to transmitter, and even over time for a single transmitter. To an extent, these deviations may also vary from bit to bit for a single transmitter. Additionally, the transmitter and receiving unit may not have clocks perfectly aligned in frequency or phase, thus increasing the difficulty in the translation. Further, properties of the communication medium may distort the transmitted signals, and a receiver utilized by the receiving unit may also cause distortion of the signals. Accordingly, systems and methods for increasing communication system reliability in view of such problems are desirable.
The present invention therefore provides systems and methods for providing clock and data recovery from digital communication signals. In one embodiment the present invention comprises is a data recovery system. A data recovery system includes means for receiving data signals and means for splitting the data signal into a plurality data channel signals and a replacement channel signal. The data channel signals are digitized by digitizers to obtain a data out signals, and the replacement channel signal is digitized by a digitizer to obtain a replacement out signal. The data out signal and the monitor out signal are compared using comparison means, the comparison means providing a result which is used to adjust the digitization of at least one of the data channel signal. The digitization of the signals occurs by comparing the signals to reference energy levels to provide an intermediate signal, and periodically sampling the intermediate signal. The comparing and sampling of the replacement channel signal is varied to determine the edges of a data eye of a data cell, and the edges of the data cell are used to determine a center of gravity of the data eye to be used as a digitization point for the data signal in the data channel. The varying of the digitization point of the replacement channel is accomplished by changing the reference energy level for the replacement channel as well as changing the phase of a clock signal used for periodically sampling the intermediate signal.
In one embodiment, the edges of the data eye are determined when a bit error rate between a data channel signal and the replacement channel out signal is greater than a predefined value.
In one embodiment a comparator is used as comparison means and a latch or a flip flop is used as a sampling means. Digital to analog convertors under the control of a controller, processor, or microprocessor generate a reference voltage for use by a comparator. Similarly, a controllable delay element, under the control of the controller, processor, or microprocessor, provides a phase adjusted version of a master clock signal which is used to vary a sampling point as a clock signal to the latch.
Many of the attendant features of this invention will be more readily appreciated as the same becomes better understood by reference to the following detailed description and considered in connection with the accompanied drawings in which like reference symbols designate like parts throughout.